FIG. 1 (Prior Art) is a simplified top-down diagram illustrative of a field programmable gate array (FPGA) integrated circuit 1. Integrated circuit 1 includes a ring of interface cells 2, an inner core of configurable logic blocks 3, and a programmable interconnect structure 4. The programmable interconnect structure 4 is configurable by a user to connect selected digital logic elements within selected configurable logic blocks together so as to realize a user-specific circuit. Digital signals are supplied to FPGA 1 via the interface cells 2 and digital signals are output from FPGA 1 via the interface cells 2. U.S. Reissue Pat. Re. No. 34,363 to Freeman describes the first FPGA and is incorporated herein by reference.
FIG. 2 (Prior Art) is a simplified top-down circuit diagram of an interface cell 5 of FPGA 1 that receives a digital signal via a bonding pad 6. According to one I/O standard, a voltage between zero and 1.5 volts is considered a digital zero whereas a voltage between 1.5 volts and 3.3 volts is considered a digital one. A comparator 7 is therefore provided to compare the digital signal on pad 6 to a 1.5 volt reference voltage VREF. The 1.5 volt reference voltage VREF is supplied to the inverting input lead 8 of comparator 7 by a reference voltage conductor 9. Reference voltage conductor 9 is a 0.28 micron wide metal trace about one millimeter long having a distributed series resistance of approximately 150,000 ohms per meter and a capacitance of approximately 250 picofarads per meter. The length of this conductor and its routing is due to its use as a low speed voltage reference conductor. It therefore has a relatively long length, high resistance, and high capacitance when compared to a high speed signal conductor.
Reference voltage conductor 9 extends parallel to an edge of FPGA 1 through many such interface cells so that the reference voltage VREF is supplied to the comparators of many such interface cells. Memory cell 10 is programmed so that transistor 11 is conductive. Memory cells 12-14 are programmed so that transistors 15-17 are nonconductive. Memory cells 18 and 19 are programmed so that comparator 7 is enabled and so that multiplexer 20 couples its upper input lead 21 to its output lead 22. A digital signal on pad 6 is therefore supplied to the noninverting input lead 23A of comparator 7 and is compared to the reference voltage VREF on conductor 9. If the magnitude of the digital signal is greater than voltage VREF, then comparator 7 outputs a digital one. This digital one passes through multiplexer 20, through programmable delay circuit 23, and to the inner core of FPGA 1 via input conductor 24. If, on the other hand, the magnitude of the digital signal on input pad 6 is less than voltage VREF, then comparator 7 outputs a digital zero and that digital zero passes to the inner core of FPGA 1 via input conductor 24.
One of the interface cells 2 is dedicated to the function of supplying the reference voltage VREF to conductor 9 for use by other interface cells. Reference voltage VREF is supplied to the pad 6 of this interface cell by an external source. Memory cell 12 of this interface cell is programmed so that transistor 15 is conductive and so that the reference voltage VREF on the pad is supplied to reference voltage conductor 9.
Interface cell 5 can also be used to output a digital signal from FPGA 1. By proper control of conductors 25-28 and memory cell 29, an enable signal is placed on enable lead 30 of output buffer 31. Output buffer 31 is therefore enabled and drives a digital signal onto pad 6. Transistor 32 is an input protection transistor, the gate of which is supplied with the supply voltage. Memory cells 13 and 14 are programmed so that one, both, or neither of transistors 16 and 17 are conductive depending on whether a pullup is desired, a pulldown is desired, or a weak keeper is desired. For additional background information on such an interface cell, see U.S. Pat. No. 5,877,632 (the subject matter of which is incorporated herein by reference).
It has been desired to incorporate analog function circuits into programmable devices and field programmable gate arrays. Such integrated circuits are often referred to as "mixed mode" circuits or "mixed signal" integrated circuits because they involve both analog function circuits and digital circuitry. Reference is made to the mixed mode integrated circuits disclosed in U.S. Pat. No. 5,107,146, U.S. Pat. No. 5,457,644, U.S. Pat. No. 5,563,526 and U.S. Pat. No. 5,821,776. Such mixed mode integrated circuits often have a digital portion where the digital functions are carried out and a separate analog portion where the analog functions are carried out.
Although such mixed mode integrated circuits may be well suited for particular applications, providing such a portion of dedicated analog circuitry may be wasteful in other applications. For example, some applications require only a small amount of analog functionality. Use of an integrated circuit with a significant amount of dedicated analog circuitry may therefore result in much of the integrated circuit not being used. Providing unused circuitry can be expensive. Alternatively, some applications require no analog functionality. In such applications, much and possibly all of the integrated circuit area used to realize the analog circuitry would be wasted. A solution is desired.